{"id":4633,"date":"2015-11-30T11:04:38","date_gmt":"2015-11-30T04:04:38","guid":{"rendered":"http:\/\/ttud.com.vn\/?p=4633"},"modified":"2017-10-02T09:54:04","modified_gmt":"2017-10-02T02:54:04","slug":"tim-hieu-ssd-flash-nand-va-controller-quyet-dinh-hieu-nang","status":"publish","type":"post","link":"https:\/\/casta.ttud.com.vn\/index.php\/tim-hieu-ssd-flash-nand-va-controller-quyet-dinh-hieu-nang\/","title":{"rendered":"T\u00ecm hi\u1ec3u SSD – Flash NAND v\u00e0 Controller quy\u1ebft \u0111\u1ecbnh hi\u1ec7u n\u0103ng"},"content":{"rendered":"

C\u00f9ng v\u1edbi s\u1ef1 ph\u00e1t tri\u1ec3n c\u1ee7a c\u00f4ng ngh\u1ec7 Flash NAND, SSD (solid-state drive) hay \u1ed5 th\u1ec3 r\u1eafn \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng ph\u1ed5 bi\u1ebfn h\u01a1n trong nhi\u1ec1u ch\u1ee7ng lo\u1ea1i thi\u1ebft b\u1ecb kh\u00e1c nhau do gi\u00e1 th\u00e0nh ng\u00e0y c\u00e0ng gi\u1ea3m trong khi dung l\u01b0\u1ee3ng t\u0103ng l\u00ean \u0111\u00e1ng k\u1ec3.<\/strong><\/p>\n

\"\"<\/p>\n

Theo h\u00e3ng nghi\u00ean c\u1ee9u th\u1ecb tr\u01b0\u1eddng IHS iSuppli d\u1ef1 \u0111o\u00e1n \u0111\u1ebfn n\u0103m 2017, SSD s\u1ebd chi\u1ebfm kho\u1ea3ng 36% th\u1ecb ph\u1ea7n thi\u1ebft b\u1ecb l\u01b0u tr\u1eef v\u1edbi kho\u1ea3ng 227 tri\u1ec7u s\u1ea3n ph\u1ea9m xu\u1ea5t x\u01b0\u1edfng. N\u1ebfu so v\u1edbi con s\u1ed1 31 tri\u1ec7u c\u1ee7a n\u0103m 2012, t\u01b0\u01a1ng \u0111\u01b0\u01a1ng v\u1edbi 6% th\u1ecb ph\u1ea7n, th\u00ec \u0111\u00e2y qu\u1ea3 l\u00e0 con s\u1ed1 \u1ea5n t\u01b0\u1ee3ng v\u00e0 c\u0169ng th\u1ec3 hi\u1ec7n r\u00f5 nhu c\u1ea7u s\u1eed d\u1ee5ng thi\u1ebft b\u1ecb l\u01b0u tr\u1eef t\u0103ng m\u1ea1nh trong nh\u1eefng n\u0103m g\u1ea7n \u0111\u00e2y.<\/p>\n

B\u00e0i vi\u1ebft chia s\u1ebb c\u1ea5u t\u1ea1o v\u00e0 c\u00e1ch th\u1ee9c ho\u1ea1t \u0111\u1ed9ng c\u1ee7a SSD \u0111\u1ec3 ch\u00fang ta hi\u1ec3u r\u00f5 h\u01a1n v\u00e0 khai th\u00e1c t\u1ed1t hi\u1ec7u n\u0103ng c\u1ee7a ch\u00fang khi s\u1eed d\u1ee5ng.<\/p>\n

V\u1ea5n \u0111\u1ec1 c\u1ee7a HDD<\/strong><\/p>\n

V\u1ec1 c\u01a1 b\u1ea3n, c\u1ea5u tr\u00fac b\u00ean trong HDD g\u1ed3m m\u1ed9t ho\u1eb7c nhi\u1ec1u phi\u1ebfn \u0111\u0129a (platter) x\u1ebfp ch\u1ed3ng l\u00ean nhau theo tr\u1ee5c \u0111\u1ee9ng. M\u1ed7i phi\u1ebfn \u0111\u0129a chia th\u00e0nh nhi\u1ec1u v\u00f2ng tr\u00f2n \u0111\u1ed3ng t\u00e2m g\u1ecdi l\u00e0 track v\u00e0 ti\u1ebfp \u0111\u00f3, m\u1ed7i track c\u0169ng \u0111\u01b0\u1ee3c chia th\u00e0nh nhi\u1ec1u \u0111o\u1ea1n nh\u1ecf g\u1ecdi l\u00e0 sector. C\u00e1c sector tr\u00ean c\u00f9ng track k\u1ebft h\u1ee3p v\u1edbi nhau th\u00e0nh cluster v\u00e0 d\u1eef li\u1ec7u \u0111\u01b0\u1ee3c l\u01b0u tr\u00ean t\u1eebng cluster. Khi c\u00f3 y\u00eau c\u1ea7u t\u1eeb h\u1ec7 th\u1ed1ng ho\u1eb7c m\u1ed9t ph\u1ea7n m\u1ec1m n\u00e0o \u0111\u00f3, \u0111\u1ea7u t\u1eeb s\u1ebd di chuy\u1ec3n qua b\u1ec1 m\u1eb7t \u0111\u0129a theo ph\u01b0\u01a1ng ngang \u0111\u1ec3 \u0111\u1ecdc ho\u1eb7c ghi d\u1eef li\u1ec7u tr\u00ean m\u1ed7i cluster.<\/p>\n

Qu\u00e1 tr\u00ecnh truy xu\u1ea5t d\u1eef li\u1ec7u \u0111\u01b0\u1ee3c g\u1ecdi l\u00e0 \u201cseeking\u201d (t\u00ecm ki\u1ebfm) v\u00e0 t\u1ed1c \u0111\u1ed9 \u0111\u1ea7u t\u1eeb di chuy\u1ec3n \u0111\u01b0\u1ee3c g\u1ecdi l\u00e0 \u201cseek time\u201d (th\u1eddi gian t\u00ecm ki\u1ebfm). V\u00ec \u0111\u1ea7u t\u1eeb lu\u00f4n ph\u1ea3i di chuy\u1ec3n \u0111\u1ebfn v\u1ecb tr\u00ed c\u1ea7n thi\u1ebft \u0111\u1ec3 \u0111\u1ecdc ho\u1eb7c ghi d\u1eef li\u1ec7u n\u00ean lu\u00f4n c\u00f3 \u0111\u1ed9 tr\u1ec5 nh\u1ea5t \u0111\u1ecbnh. Tr\u01b0\u1eddng h\u1ee3p d\u1eef li\u1ec7u b\u1ecb ph\u00e2n m\u1ea3nh, t\u1ee9c l\u01b0u r\u1eddi r\u1ea1c \u1edf nhi\u1ec1u v\u1ecb tr\u00ed kh\u00e1c nhau, \u0111\u1ea7u t\u1eeb s\u1ebd ph\u1ea3i di chuy\u1ec3n nhi\u1ec1u h\u01a1n c\u0169ng nh\u01b0 ph\u1ea3i ch\u1edd phi\u1ebfn \u0111\u0129a quay \u0111\u1ebfn v\u1ecb tr\u00ed ph\u00f9 h\u1ee3p \u0111\u1ec3 ho\u00e0n t\u1ea5t c\u00e2u l\u1ec7nh th\u1ef1c thi. Th\u1eadm ch\u00ed n\u1ebfu \u1ed5 c\u1ee9ng \u0111ang \u1edf tr\u1ea1ng th\u1eddi ch\u1edd, c\u00e1c phi\u1ebfn \u0111\u0129a ng\u1eebng quay th\u00ec \u0111\u1ed9 tr\u1ec5 s\u1ebd cao h\u01a1n r\u1ea5t nhi\u1ec1u.<\/p>\n

C\u00e1c nh\u00e0 s\u1ea3n xu\u1ea5t \u0111\u00e3 t\u00edch h\u1ee3p c\u00f4ng ngh\u1ec7 NCQ (Native Command Queuing) c\u00f3 ch\u1ee9c n\u0103ng ph\u00e2n t\u00edch, s\u1eafp x\u1ebfp c\u00e1c c\u00e2u l\u1ec7nh c\u1ea7n th\u1ef1c thi \u0111\u1ec3 t\u1ed1i \u01b0u vi\u1ec7c truy xu\u1ea5t d\u1eef li\u1ec7u t\u1eeb \u1ed5 c\u1ee9ng c\u1ee7a nhi\u1ec1u ti\u1ec7n \u00edch, \u1ee9ng d\u1ee5ng c\u00f9ng l\u00fac trong m\u00f4i tr\u01b0\u1eddng \u0111a nhi\u1ec7m. \u0110i\u1ec1u n\u00e0y ch\u1ec9 c\u1ea3i thi\u1ec7n ch\u1ee9 ch\u01b0a th\u1ec3 kh\u1eafc ph\u1ee5c ho\u00e0n to\u00e0n v\u1ea5n \u0111\u1ec1 \u0111\u1ed9 tr\u1ec5 khi \u0111\u1ecdc, ghi d\u1eef li\u1ec7u. M\u1ed9t v\u1ea5n \u0111\u1ec1 n\u1eefa l\u00e0 kh\u1ea3 n\u0103ng ch\u1ed1ng s\u1ed1c. Khi \u1ed5 c\u1ee9ng \u0111ang ho\u1ea1t \u0111\u1ed9ng \u1edf t\u1ed1c \u0111\u1ed9 cao ch\u1ec9 m\u1ed9t t\u00e1c \u0111\u1ed9ng nh\u1ecf l\u00ean n\u00f3 l\u00e0 c\u00f3 th\u1ec3 g\u00e2y h\u1eadu qu\u1ea3 kh\u00f4n l\u01b0\u1eddng.<\/p>\n

T\u1ed1c \u0111\u1ed9 truy xu\u1ea5t d\u1eef li\u1ec7u nhanh nh\u1ea5t c\u1ee7a \u1ed5 c\u1ee9ng c\u00f3 th\u1ec3 \u0111\u1ea1t 200 MB\/s v\u00e0 th\u1eddi gian truy c\u1eadp ng\u1eabu nhi\u00ean t\u1eeb 5 \u2013 8 ms. T\u00ednh theo t\u1ef7 l\u1ec7 gi\u1eefa dung l\u01b0\u1ee3ng v\u00e0 chi ph\u00ed t\u00ednh tr\u00ean m\u1ed7i gigabyte th\u00ec \u1ed5 c\u1ee9ng truy\u1ec1n th\u1ed1ng v\u1eabn l\u00e0 l\u1ef1a ch\u1ecdn h\u00e0ng \u0111\u1ea7u.<\/p>\n

\u01afu th\u1ebf c\u1ee7a SSD<\/strong><\/p>\n

Kh\u00f4ng ch\u1ec9 m\u1edf r\u1ed9ng dung l\u01b0\u1ee3ng l\u01b0u tr\u1eef v\u00e0 chi ph\u00ed s\u1ea3n xu\u1ea5t ng\u00e0y c\u00e0ng th\u1ea5p h\u01a1n, SSD c\u00f2n h\u1ea5p d\u1eabn ng\u01b0\u1eddi d\u00f9ng do c\u00f3 \u01b0u th\u1ebf k\u00edch th\u01b0\u1edbc nh\u1ecf g\u1ecdn, t\u1ed1c \u0111\u1ed9 truy xu\u1ea5t d\u1eef li\u1ec7u v\u01b0\u1ee3t tr\u1ed9i, \u0111\u1ed9 tin c\u1eady cao h\u01a1n v\u00e0 nh\u1ea5t l\u00e0 kh\u1ea3 n\u0103ng ch\u1ed1ng s\u1ed1c t\u1ed1t h\u01a1n v\u00ec kh\u00f4ng c\u00f3 b\u1ed9 ph\u1eadn chuy\u1ec3n \u0111\u1ed9ng.<\/p>\n

Kh\u00e1c v\u1edbi \u1ed5 c\u1ee9ng truy\u1ec1n th\u1ed1ng, SSD kh\u00f4ng l\u01b0u d\u1eef li\u1ec7u tr\u00ean c\u00e1c phi\u1ebfn \u0111\u0129a v\u00e0 ho\u00e0n to\u00e0n kh\u00f4ng s\u1eed d\u1ee5ng \u0111\u1ea7u \u0111\u1ecdc. Thay v\u00e0o \u0111\u00f3, d\u1eef li\u1ec7u s\u1ebd \u0111\u01b0\u1ee3c l\u01b0u tr\u00ean c\u00e1c chip nh\u1edb ki\u1ebfn tr\u00fac NAND hay c\u00f2n \u0111\u01b0\u1ee3c bi\u1ebft \u0111\u1ebfn d\u01b0\u1edbi t\u00ean g\u1ecdi flash NAND. C\u1ea5u t\u1ea1o c\u1ee7a flash NAND bao g\u1ed3m nhi\u1ec1u b\u00f3ng b\u00e1n d\u1eabn (transitor) \u0111\u1eb7c bi\u1ec7t c\u00f3 t\u00ean g\u1ecdi floating gate transistor, \u0111\u01b0\u1ee3c thi\u1ebft k\u1ebf \u0111\u1ec3 c\u00f3 th\u1ec3 gi\u1eef nguy\u00ean tr\u1ea1ng th\u00e1i c\u1ea3 khi kh\u00f4ng c\u1ea5p ngu\u1ed3n. \u0110\u00e2y c\u0169ng l\u00e0 \u0111i\u1ec3m kh\u00e1c bi\u1ec7t v\u1edbi chip flash d\u00f9ng trong b\u1ed9 nh\u1edb DRAM, v\u1ed1n c\u1ea7n ph\u1ea3i l\u00e0m t\u01b0\u01a1i nhi\u1ec1u l\u1ea7n m\u1ed7i gi\u00e2y v\u00e0 kh\u00f4ng l\u01b0u d\u1eef li\u1ec7u khi m\u1ea5t ngu\u1ed3n.<\/p>\n

Trong ph\u1ea7n ti\u1ebfp theo, ch\u00fang ta s\u1ebd t\u00ecm hi\u1ec3u hai th\u00e0nh ph\u1ea7n quan tr\u1ecdng nh\u1ea5t quy\u1ebft \u0111\u1ecbnh hi\u1ec7u su\u1ea5t SSD l\u00e0 flash NAND v\u00e0 vi m\u1ea1ch \u0111i\u1ec1u khi\u1ec3n hay c\u00f2n g\u1ecdi controller.<\/p>\n

NAND SLC, MLC hay TLC<\/strong><\/p>\n

B\u1ea3ng so s\u00e1nh th\u00f4ng s\u1ed1 k\u1ef9 thu\u1eadt c\u1ee7a flash NAND SLC, MLC, TLC v\u00e0 RAM.\u200b<\/em><\/p>\n

C\u00f3 ba c\u00f4ng ngh\u1ec7 flash NAND hi\u1ec7n \u0111ang s\u1eed d\u1ee5ng ph\u1ed5 bi\u1ebfn trong SSD l\u00e0 SLC (single-level cell), MLC (multi-level cell) v\u00e0 TLC (triple-level cell). S\u1ef1 kh\u00e1c nhau gi\u1eefa c\u00e1c c\u00f4ng ngh\u1ec7 n\u00e0y l\u00e0 m\u1eadt \u0111\u1ed9 bit d\u1eef li\u1ec7u ch\u1ee9a trong chip nh\u1edb, \u0111\u1ed9 tr\u1ec5 v\u00e0 \u0111\u1ed9 b\u1ec1n d\u1ef1a theo chu k\u1ef3 ghi x\u00f3a (P\/E cycle). V\u00e0 \u0111i\u1ec1u n\u00e0y \u1ea3nh h\u01b0\u1edfng tr\u1ef1c ti\u1ebfp \u0111\u1ebfn hi\u1ec7u n\u0103ng t\u1ed5ng th\u1ec3 c\u1ee7a SSD.<\/p>\n

Theo b\u1ea3ng th\u00f4ng s\u1ed1 k\u1ef9 thu\u1eadt b\u00ean d\u01b0\u1edbi cho th\u1ea5y NAND SLC ch\u1ec9 ch\u1ee9a 1 bit d\u1eef li\u1ec7u (0 ho\u1eb7c 1) nh\u01b0ng c\u00f3 \u0111\u1ed9 tr\u1ec5 th\u1ea5p nh\u1ea5t v\u00e0 \u0111\u1ed9 b\u1ec1n \u0111\u1ea1t \u0111\u1ebfn 100.000 chu k\u1ef3 ghi x\u00f3a. MLC ch\u1ee9a 2 bit d\u1eef li\u1ec7u v\u00e0 chu k\u1ef3 ghi x\u00f3a v\u00e0o kho\u1ea3ng 10.000 l\u1ea7n. Trong khi \u0111\u00f3, NAND TLC (triple level cell) ch\u1ee9a \u0111\u1ebfn 3 bit d\u1eef li\u1ec7u nh\u01b0ng v\u1ea5n \u0111\u1ec1 l\u1edbn nh\u1ea5t c\u1ee7a c\u00f4ng ngh\u1ec7 chip nh\u1edb n\u00e0y l\u00e0 \u0111\u1ed9 tin c\u1eady th\u1ea5p, ch\u1ec9 5.000 chu k\u1ef3 P\/E v\u00e0 \u0111\u1ed9 tr\u1ec5 cao h\u01a1n nhi\u1ec1u so v\u1edbi hai lo\u1ea1i tr\u00ean.<\/p>\n

V\u1ec1 c\u01a1 b\u1ea3n, SSD s\u1eed d\u1ee5ng chip NAND TLC c\u00f3 t\u1ed1c \u0111\u1ed9 \u0111\u1ecdc l\u1eabn ghi th\u1ea5p h\u01a1n chip MLC, m\u1eb7c d\u00f9 m\u1ed7i cell c\u1ee7a TLC ch\u1ee9a \u0111\u1ebfn 3 bit d\u1eef li\u1ec7u. Ng\u01b0\u1ee3c l\u1ea1i SSD d\u00f9ng NAND SLC c\u00f3 hi\u1ec7u n\u0103ng v\u00e0 \u0111\u1ed9 b\u1ec1n cao nh\u1ea5t \u0111\u1ed3ng th\u1eddi chi ph\u00ed s\u1ea3n xu\u1ea5t c\u0169ng c\u0169ng \u0111\u1eaft h\u01a1n nhi\u1ec1u, n\u00ean ch\u1ec9 \u1ee9ng d\u1ee5ng trong c\u00e1c h\u1ec7 th\u1ed1ng \u0111\u00f2i h\u1ecfi \u0111\u1ed9 b\u1ec1n v\u00e0 kh\u1ea3 n\u0103ng \u0111\u00e1p \u1ee9ng c\u00f9ng l\u00fac s\u1ed1 l\u01b0\u1ee3t truy xu\u1ea5t d\u1eef li\u1ec7u l\u1edbn.<\/p>\n

V\u1ec1 c\u1ea5u tr\u00fac flash NAND \u0111\u01b0\u1ee3c chia theo m\u00f4 h\u00ecnh l\u01b0\u1edbi, c\u01a1 b\u1ea3n l\u00e0 cell (\u00f4 nh\u1edb), page (trang) v\u00e0 block (kh\u1ed1i). Nhi\u1ec1u cell h\u1ee3p th\u00e0nh m\u1ed9t page, k\u00edch th\u01b0\u1edbc th\u01b0\u1eddng t\u1eeb 2 – 16KB. T\u01b0\u01a1ng t\u1ef1 nhi\u1ec1u page s\u1ebd t\u1ea1o th\u00e0nh m\u1ed9t block, g\u1ed3m 128 \u0111\u1ebfn 256 page v\u1edbi k\u00edch th\u01b0\u1edbc t\u1eeb 256KB – 4MB. Trong xu h\u01b0\u1edbng hi\u1ec7n nay, nhi\u1ec1u nh\u00e0 s\u1ea3n xu\u1ea5t th\u01b0\u1eddng ch\u1ecdn c\u00e1ch m\u1edf r\u1ed9ng k\u00edch th\u01b0\u1edbc page v\u00e0 block \u0111\u1ec3 t\u0103ng t\u1ed1c \u0111\u1ed9 ghi c\u1ee7a SSD.<\/p>\n

C\u01a1 ch\u1ebf ho\u1ea1t \u0111\u1ed9ng c\u1ee7a flash NAND<\/strong>
\nH\u00ecnh minh h\u1ecda tr\u00ean cho th\u1ea5y trong c\u1ea5u t\u1ea1o floating gate transistor c\u00f3 m\u1ed9t c\u1ed5ng \u0111\u1ed9ng (floating gate) n\u1eb1m gi\u1eefa c\u1ed5ng \u0111i\u1ec1u khi\u1ec3n (control gate) v\u00e0 \u0111\u1ebf silicon b\u00ean d\u01b0\u1edbi. \u0110\u00e2y c\u0169ng l\u00e0 n\u01a1i l\u01b0u m\u1ed9t trong hai tr\u1ea1ng th\u00e1i l\u00e0 l\u1eadp tr\u00ecnh ho\u1eb7c x\u00f3a \u0111\u1ec3 bi\u1ec3u th\u1ecb m\u1ed9t hai gi\u00e1 tr\u1ecb c\u01a1 b\u1ea3n l\u00e0 0 ho\u1eb7c 1 trong h\u1ec7 nh\u1ecb ph\u00e2n. Ph\u1ee7 quanh floating gate l\u00e0 m\u1ed9t l\u1edbp m\u1ecfng ch\u1ea5t li\u1ec7u c\u00e1ch \u0111i\u1ec7n nh\u01b0 dioxide silicon.<\/p>\n

\u1ede tr\u1ea1ng th\u00e1i b\u00ecnh th\u01b0\u1eddng, gi\u1eefa c\u1ef1c ngu\u1ed3n (source line) v\u00e0 c\u1ef1c d\u1eabn (bit line) kh\u00f4ng xu\u1ea5t hi\u1ec7n d\u00f2ng \u0111i\u1ec7n. Khi \u0111\u1eb7t \u0111i\u1ec7n \u00e1p d\u01b0\u01a1ng v\u00e0o c\u1ed5ng \u0111i\u1ec1u khi\u1ec3n th\u00ec gi\u1eefa c\u1ef1c d\u1eabn v\u00e0 c\u1ef1c ngu\u1ed3n s\u1ebd h\u00ecnh th\u00e0nh d\u00f2ng \u0111i\u1ec7n v\u00e0 \u0111\u1ea9y electron t\u1eeb \u0111\u1ebf silicon b\u00ean d\u01b0\u1edbi qua l\u1edbp c\u00e1ch \u0111i\u1ec7n \u0111i v\u00e0o c\u1ed5ng \u0111\u1ed9ng. Nh\u1edd v\u1eady tr\u1ea1ng th\u00e1i c\u1ee7a c\u1ed5ng \u0111\u1ed9ng c\u00f3 th\u1ec3 \u0111\u01b0\u1ee3c x\u00e1c \u0111\u1ecbnh d\u1ef1a tr\u00ean s\u1ef1 thay \u0111\u1ed5i \u0111i\u1ec7n \u00e1p ng\u01b0\u1ee1ng.<\/p>\n

V\u1edbi NAND SLC ch\u1ec9 c\u00f3 hai m\u1ee9c tr\u1ea1ng th\u00e1i l\u00e0 l\u1eadp tr\u00ecnh ho\u1eb7c x\u00f3a trong khi MLC c\u00f3 \u0111\u1ebfn b\u1ed1n m\u1ee9c v\u00e0 TLC l\u00e0 t\u00e1m m\u1ee9c tr\u1ea1ng th\u00e1i \u0111i\u1ec7n \u00e1p ng\u01b0\u1ee1ng. V\u1ec1 m\u1eb7t l\u00fd thuy\u1ebft, \u0111\u1ec3 m\u1ed9t cell bi\u1ec3u di\u1ec5n \u0111\u01b0\u1ee3c \u0111\u01b0\u1ee3c n bit nh\u1ecb ph\u00e2n th\u00ec n\u00f3 ph\u1ea3i \u0111\u01b0\u1ee3c thi\u1ebft k\u1ebf \u0111\u1ea1t 2n tr\u1ea1ng th\u00e1i kh\u00e1c nhau. \u1ee8ng v\u1edbi m\u1ed7i tr\u1ea1ng th\u00e1i, floating gate s\u1ebd c\u00f3 m\u1ed9t gi\u00e1 tr\u1ecb \u0111i\u1ec7n \u00e1p ng\u01b0\u1ee1ng.<\/p>\n

SSD_tinhte 8. \u200b<\/p>\n

S\u1edf d\u0129 NAND TLC c\u00f3 t\u1ed1c \u0111\u1ed9 ch\u1eadm h\u01a1n MLC v\u00e0 SLC l\u00e0 do n\u00f3 l\u01b0u tr\u1eef nhi\u1ec1u bit d\u1eef li\u1ec7u h\u01a1n. \u0110\u1ed1i v\u1edbi SLC th\u00ec chip \u0111i\u1ec1u khi\u1ec3n (controller) ch\u1ec9 quan t\u00e2m \u0111\u1ebfn hai m\u1ee9c l\u00e0 0 ho\u1eb7c 1 (t\u01b0\u01a1ng \u1ee9ng v\u1edbi l\u1eadp tr\u00ecnh ho\u1eb7c x\u00f3a). NAND MLC th\u00ec m\u1ed7i cell ch\u1ee9a nhi\u1ec1u h\u01a1n, c\u00f3 4 gi\u00e1 tr\u1ecb l\u00e0 00, 01, 10 ho\u1eb7c 11 trong khi NAND TLC l\u1ea1i ch\u1ee9a \u0111\u1ebfn 8 gi\u00e1 tr\u1ecb. Vi\u1ec7c \u0111\u1ecdc d\u1eef li\u1ec7u trong m\u1ed7i \u00f4 nh\u1edb s\u1ebd do b\u1ed9 \u0111i\u1ec1u khi\u1ec3n qu\u1ea3n l\u00fd th\u00f4ng qua m\u1ee9c \u0111i\u1ec7n \u00e1p ng\u01b0\u1ee1ng.<\/p>\n

V\u1edbi NAND MLC v\u00e0 TLC, c\u00f3 ba y\u1ebfu t\u1ed1 c\u1ea7n \u0111\u1ea3m b\u1ea3o l\u00e0:<\/p>\n

– Electron n\u1ea1p \u0111\u00fang v\u1ecb tr\u00ed. Qu\u00e1 tr\u00ecnh l\u1eadp tr\u00ecnh \u00f4 nh\u1edb \u0111\u00f2i h\u1ecfi s\u1ef1 ch\u00ednh x\u00e1c cao n\u00ean c\u1ea7n ki\u1ec3m so\u00e1t t\u1ed1t t\u1eeb c\u1ea5p v\u1eadt l\u00fd, nh\u1ea5t l\u00e0 y\u1ebfu t\u1ed1 th\u1eddi gian v\u00e0 m\u1ee9c \u0111i\u1ec7n \u00e1p n\u1ea1p.<\/em><\/p>\n

– S\u1ef1 ch\u00ednh x\u00e1c. Qu\u00e1 tr\u00ecnh \u0111\u1ecdc d\u1eef li\u1ec7u trong c\u00f4ng ngh\u1ec7 MLC v\u00e0 TLC th\u1ef1c ch\u1ea5t l\u00e0 qu\u00e1 tr\u00ecnh chuy\u1ec3n \u0111\u1ed5i gi\u00e1 tr\u1ecb t\u1eeb d\u1ea1ng t\u01b0\u01a1ng t\u1ef1 (analog) sang d\u1ea1ng s\u1ed1 (digital) n\u00ean ph\u00e9p \u0111\u1ecdc gi\u00e1 tr\u1ecb \u0111i\u1ec7n \u00e1p \u00f4 nh\u1edb c\u1ea7n s\u1ef1 ch\u00ednh x\u00e1c cao. N\u1ebfu kh\u00f4ng, d\u1eef li\u1ec7u c\u00f3 th\u1ec3 sai l\u1ec7ch v\u00e0 g\u00e2y l\u1ed7i.<\/em><\/p>\n

– T\u00ednh \u1ed5n \u0111\u1ecbnh tr\u1ea1ng th\u00e1i n\u1ea1p. \u0110\u1ea3m b\u1ea3o t\u1ef7 l\u1ec7 th\u1ea5t tho\u00e1t trong c\u1ed5ng \u0111\u1ed9ng kh\u00f4ng v\u01b0\u1ee3t qu\u00e1 1 electron\/ng\u00e0y. \u0110i\u1ec1u n\u00e0y cho th\u1ea5y SSD v\u1eabn c\u00f3 nguy c\u01a1 m\u1ea5t d\u1eef li\u1ec7u n\u1ebfu b\u1ea1n kh\u00f4ng s\u1eed d\u1ee5ng ch\u00fang trong m\u1ed9t th\u1eddi gian d\u00e0i, \u0111\u1eb7c bi\u1ec7t l\u00e0 r\u1ee7i ro n\u00e0y c\u00e0ng t\u0103ng trong m\u00f4i tr\u01b0\u1eddng nhi\u1ec7t \u0111\u1ed9 cao.<\/em><\/p>\n

T\u1ed1c \u0111\u1ed9 \u0111\u1ecdc, ghi v\u00e0 x\u00f3a<\/strong><\/p>\n

M\u1ed9t trong nh\u1eefng h\u1ea1n ch\u1ebf c\u1ee7a SSD l\u00e0 t\u1ed1c \u0111\u1ed9 \u0111\u1ecdc v\u00e0 ghi tr\u00ean cell tr\u1ed1ng r\u1ea5t nhanh nh\u01b0ng l\u1ea1i gi\u1ea3m \u0111\u00e1ng k\u1ec3 trong l\u1ea7n ghi d\u1eef li\u1ec7u k\u1ebf ti\u1ebfp. Nguy\u00ean nh\u00e2n n\u1eb1m \u1edf c\u01a1 ch\u1ebf ho\u1ea1t \u0111\u1ed9ng c\u1ee7a SSD v\u00e0 c\u1ea5u tr\u00fac flash NAND. Kh\u00e1c v\u1edbi \u1ed5 c\u1ee9ng truy\u1ec1n th\u1ed1ng, SSD \u0111\u1ecdc v\u00e0 ghi d\u1eef li\u1ec7u theo t\u1eebng page nh\u01b0ng ch\u1ec9 c\u00f3 th\u1ec3 x\u00f3a d\u1eef li\u1ec7u theo t\u1eebng block. Trong khi \u0111\u00f3, v\u1ea5n \u0111\u1ec1 c\u1ee7a flash NAND l\u00e0 kh\u00f4ng cho ph\u00e9p ghi \u0111\u00e8 d\u1eef li\u1ec7u tr\u1ef1c ti\u1ebfp l\u00ean cell c\u0169 m\u00e0 ph\u1ea3i qua b\u01b0\u1edbc x\u00f3a d\u1eef li\u1ec7u tr\u01b0\u1edbc ti\u00ean.<\/p>\n

Khi b\u1ea1n x\u00f3a d\u1eef li\u1ec7u, chip \u0111i\u1ec1u khi\u1ec3n ch\u1ec9 \u0111\u01a1n gi\u1ea3n \u0111\u00e1nh d\u1ea5u c\u00e1c page \u0111\u00f3 ch\u1ee9 kh\u00f4ng th\u1ef1c s\u1ef1 x\u00f3a ch\u00fang cho \u0111\u1ebfn khi \u0111\u00e3 c\u1ea7n s\u1eed d\u1ee5ng l\u1ea1i. \u0110i\u1ec1u n\u00e0y c\u0169ng gi\u1ea3i th\u00edch t\u1ea1i sao SSD c\u00e0ng s\u1eed d\u1ee5ng l\u00e2u, hi\u1ec7u n\u0103ng c\u00e0ng gi\u1ea3m. Trong m\u1ed9t block b\u1ed9 nh\u1edb c\u00f3 th\u1ec3 t\u1ed3n t\u1ea1i c\u00e1c page \u0111ang ch\u1ee9a d\u1eef li\u1ec7u l\u1eabn m\u1ed9t s\u1ed1 page \u1edf tr\u1ea1ng th\u00e1i ch\u1edd x\u00f3a. \u0110\u1ec3 d\u1ecdn d\u1eb9p, chip \u0111i\u1ec1u khi\u1ec3n s\u1ebd ch\u00e9p d\u1eef li\u1ec7u sang m\u1ed9t block m\u1edbi v\u00e0 x\u00f3a to\u00e0n b\u1ed9 block c\u0169, s\u1eb5n s\u00e0ng cho m\u1ed9t chu k\u1ef3 s\u1eed d\u1ee5ng m\u1edbi. Qu\u00e1 tr\u00ecnh n\u00e0y \u0111\u01b0\u1ee3c g\u1ecdi l\u00e0 garbage collection (t\u1ea1m d\u1ecbch thu gom r\u00e1c).<\/p>\n

Trong b\u00e0i vi\u1ebft ti\u1ebfp theo, m\u00ecnh s\u1ebd \u0111\u1ec1 c\u1eadp m\u1ed9t th\u00e0nh ph\u1ea7n quan tr\u1ecdng kh\u00f4ng k\u00e9m l\u00e0 controller v\u00e0 m\u1ed9t s\u1ed1 ch\u1ee9c n\u0103ng h\u1ed7 tr\u1ee3 c\u1ee7a SSD nh\u1eb1m t\u1ed1i \u01b0u t\u1ed1c \u0111\u1ed9 v\u00e0 \u0111\u1ed9 b\u1ec1n trong qu\u00e1 tr\u00ecnh s\u1eed d\u1ee5ng.<\/p>\n

Ngu\u1ed3n tham kh\u1ea3o: Extremetech.com, Howstuffworks.com, Cnet.com\u200b<\/em><\/strong><\/p>\n

Ngu\u1ed3n tinhte.vn<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

C\u00f9ng v\u1edbi s\u1ef1 ph\u00e1t tri\u1ec3n c\u1ee7a c\u00f4ng ngh\u1ec7 Flash NAND, SSD (solid-state drive) hay \u1ed5 th\u1ec3 r\u1eafn \u0111\u01b0\u1ee3c s\u1eed d\u1ee5ng ph\u1ed5 bi\u1ebfn h\u01a1n trong nhi\u1ec1u ch\u1ee7ng lo\u1ea1i thi\u1ebft b\u1ecb kh\u00e1c nhau do gi\u00e1 th\u00e0nh ng\u00e0y c\u00e0ng gi\u1ea3m trong khi dung l\u01b0\u1ee3ng t\u0103ng l\u00ean \u0111\u00e1ng k\u1ec3. Theo h\u00e3ng nghi\u00ean c\u1ee9u th\u1ecb tr\u01b0\u1eddng IHS iSuppli d\u1ef1 \u0111o\u00e1n […]<\/p>\n","protected":false},"author":17,"featured_media":5111,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[47],"tags":[],"class_list":["post-4633","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-tin-tuc"],"_links":{"self":[{"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/posts\/4633","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/users\/17"}],"replies":[{"embeddable":true,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/comments?post=4633"}],"version-history":[{"count":3,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/posts\/4633\/revisions"}],"predecessor-version":[{"id":5112,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/posts\/4633\/revisions\/5112"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/media\/5111"}],"wp:attachment":[{"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/media?parent=4633"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/categories?post=4633"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/casta.ttud.com.vn\/index.php\/wp-json\/wp\/v2\/tags?post=4633"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}